1. Technical Field
The present invention relates to a semiconductor device, and more particularly, to a synchronous mirror delay circuit and a semiconductor integrated circuit device having the same.
2. Discussion of the Related Art
With the advance of complementary metal oxide semiconductor (CMOS) integrated circuit technology, an operating speed of an integrated circuit has been improved. In order to increase the operating speed of the integrated circuit, it is typically necessary to improve a clock signal used for driving the integrated circuit. This is accomplished by increasing a clock frequency of the clock signal. Among the problems that result due to increasing the clock signal's frequency, is a clock skew that occurs between an external clock signal and an internal clock signal. The resulting clock skew should be fixed because it can cause the integrated circuit to operate erroneously. Generally, a phase locked loop (PLL) circuit or a delay locked loop (DLL) circuit has been used to solve the clock skew. However, such circuits have a drawback in that a synchronization time is long. In order to solve this drawback, a synchronous mirror delay (SMD) circuit has been proposed. Existing SMD circuits generate an internal clock signal that is synchronized with an external clock signal in only two cycles.
Typical SMD circuits are disclosed in U.S. Pat. No. 6,060,920, entitled “MULTIPLEX SYNCHRONOUS DELAY CIRCUIT”, and U.S. Pat. No. 6,373,913, entitled “INTERNAL CLOCK SIGNAL GENERATOR INCLUDING CIRCUIT FOR ACCURATELY SYNCHRONIZING INTERNAL CLOCK SIGNAL WITH EXTERNAL CLOCK SIGNAL”.
The common clock generating circuits, such as SMD, PLL and DLL circuits, have predetermined synchronization ranges in which they typically operate. These clock generating circuits do not, however, operate properly when in a low frequency band out of their synchronization ranges. For example, as the operating frequency of an integrated circuit increases, an operating frequency of its associated test equipment does not increase in proportion to the increase in the operating frequency of the integrated circuit. This makes it difficult to test a high-speed semiconductor integrated circuit device by means of conventional test equipment operating at lower frequencies.
Accordingly, there is a need for a device that allows a high-speed semiconductor integrated circuit to operate normally when in a frequency band out of its synchronization range.